The present invention relates to techniques for compensating for parasitic capacitance associated with the gain resistors of an operational amplifier circuit, and in particular compensating for the extra phase shift introduced by the parasitic poles due to this parasitic capacitance.
FIG. 1 illustrates a resistive gain amplifier circuit having an operational amplifier 10 with resistors R1, R2, R3 and R4 connected between a voltage input 12 and a voltage output 14. A switch 16 determines a connection to the inverting input of operational amplifier 10 between a point A (between R4 and R3), a point B (between R3 and R2), and a point C (between R2 and R1). Depending upon which position is selected, the gain of the amplifier is varied accordingly. Each of the resistors, when constructed on a semiconductor chip, will have associated parasitic capacitance between the resistor and the substrate. These parasitic capacitances are modeled in the circuit of FIG. 1 as capacitors between the resistor and ground (since the substrate is grounded). Thus, resistor R4 has parasitic capacitance C42 and C41. Resistor R3 has parasitic capacitance C32 and C31. Resistor R2 has parasitic capacitance C22 and C21. Resistor R1 has parasitic capacitance C12 and C11. Also shown in FIG. 1 are the load resistance and capacitance, RL and CL, connected to ground.
A problem with the circuit of FIG. 1 is that for high-frequency gain, the parasitic capacitances cause a degradation of the phase margin to the point of instability, rendering such high gain stages difficult to frequency compensate.
Depending on the type of resistor material, i.e., diffusion or polysilicon, the capacitors are either junction capacitors or polysilicon-to-substrate capacitances. These capacitances, together with the resistors, introduce additional phase shift in the feedback loop, degrading the phase margin and frequency stability of the operational amplifier. The effect on the phase margin becomes more severe for larger resistors or wider band amplifiers as the extra poles due to these resistor/capacitor (RC) circuits are pulled into the bandwidth of the amplifier.
One approach to dealing with a parasitic capacitance or resistor is shown in U.S. Pat. No. 6,472,942. This patent adds a parallel capacitance in order to compensate for the parasitic substrate capacitance. In other words, this patent attempts to create a zero to compensate for the pole induced by the parasitic capacitance. A similar approach is shown in U.S. Pat. No. 6,005,280. Here, a resistor is shown extending over two different n-wells. One of the n-wells is connected to ground, and the other is connected to the output. Again, this attempts to put a zero on top of a pole in order to compensate for the parasitic capacitance.
U.S. Pat. No. 5,880,634 also shows a method for compensating for the parasitic capacitance by canceling out the parasitic capacitance. This is done by including a compensation capacitor Cc adding a value equal to ⅙ of the parasitic capacitance.